https://wiki.kicad.jp/index.php?title=Pcbnew_chap4_JA&feed=atom&action=historyPcbnew chap4 JA - 版の履歴2024-03-28T10:59:16Zこのウィキのこのページに関する変更履歴MediaWiki 1.36.2https://wiki.kicad.jp/index.php?title=Pcbnew_chap4_JA&diff=181&oldid=prev2012年8月2日 (木) 02:06にNenokuniによる2012-08-02T02:06:11Z<p></p>
<a href="https://wiki.kicad.jp/index.php?title=Pcbnew_chap4_JA&diff=181&oldid=167">差分を表示</a>Nenokunihttps://wiki.kicad.jp/index.php?title=Pcbnew_chap4_JA&diff=167&oldid=prev2012年7月27日 (金) 14:02にMilloによる2012-07-27T14:02:24Z<p></p>
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<td colspan="2" style="background-color: #fff; color: #202122; text-align: center;">2012年7月27日 (金) 14:02時点における版</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l1">1行目:</td>
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<tr><td colspan="2"></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">>>[[翻訳作業ページ]] ([[Pcbnew_chap3_JA|前ページ]]/[[Pcbnew_chap5_JA|次ページ]])</ins></div></td></tr>
<tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>= Schematic Implementation =</div></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>= Schematic Implementation =</div></td></tr>
<tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>== Linking a schematic to a printed circuit board ==</div></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>== Linking a schematic to a printed circuit board ==</div></td></tr>
<tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l5">5行目:</td>
<td colspan="2" class="diff-lineno">6行目:</td></tr>
<tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The netlist file, generated from the schematic is usually missing the footprint modules that correspond to the various components. Consequently an intermediate stage is necessary. During this intermediate process the association components/modules is performed. In KiCad, CvPcb is used to create this association and a file named * .cmp is produced. CvPcb also updates the netlist file using this information.</div></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>The netlist file, generated from the schematic is usually missing the footprint modules that correspond to the various components. Consequently an intermediate stage is necessary. During this intermediate process the association components/modules is performed. In KiCad, CvPcb is used to create this association and a file named * .cmp is produced. CvPcb also updates the netlist file using this information.</div></td></tr>
<tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br/></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br/></td></tr>
<tr><td class="diff-marker" data-marker="−"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>Cvppcb can also output a <del style="font-weight: bold; text-decoration: none;">。ネstuff file。ノ </del>*.stf which can be back annotated into the schematic file as the F2 field for each component, saving the task of re-assigning module footprints in each schematic edit pass. In Eeschema copying a component will also copy the footprint assignment and set the reference designator as unassigned for later auto-incremental-annotation.</div></td><td class="diff-marker" data-marker="+"></td><td style="color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>Cvppcb can also output a <ins style="font-weight: bold; text-decoration: none;">"stuff file" </ins>*.stf which can be back annotated into the schematic file as the F2 field for each component, saving the task of re-assigning module footprints in each schematic edit pass. In Eeschema copying a component will also copy the footprint assignment and set the reference designator as unassigned for later auto-incremental-annotation.</div></td></tr>
<tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br/></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><br/></td></tr>
<tr><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Pcbnew reads the modified netlist file .net and, if it exists, the .cmp file</div></td><td class="diff-marker"></td><td style="background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;"><div>Pcbnew reads the modified netlist file .net and, if it exists, the .cmp file</div></td></tr>
</table>Millohttps://wiki.kicad.jp/index.php?title=Pcbnew_chap4_JA&diff=158&oldid=prevMillo: 原文(writerでmediawiki形式でエクスポート)2012-07-27T13:36:40Z<p>原文(writerでmediawiki形式でエクスポート)</p>
<p><b>新規ページ</b></p><div>= Schematic Implementation =<br />
== Linking a schematic to a printed circuit board ==<br />
Generally speaking, a schematic sheet is linked to its printed circuit board by means of the netlist file, which is normally generated by the schematic editor used to make the schematic. Pcbnew accepts netlist files made with Eeschema or Orcad PCB 2.<br />
<br />
The netlist file, generated from the schematic is usually missing the footprint modules that correspond to the various components. Consequently an intermediate stage is necessary. During this intermediate process the association components/modules is performed. In KiCad, CvPcb is used to create this association and a file named * .cmp is produced. CvPcb also updates the netlist file using this information.<br />
<br />
Cvppcb can also output a 。ネstuff file。ノ *.stf which can be back annotated into the schematic file as the F2 field for each component, saving the task of re-assigning module footprints in each schematic edit pass. In Eeschema copying a component will also copy the footprint assignment and set the reference designator as unassigned for later auto-incremental-annotation.<br />
<br />
Pcbnew reads the modified netlist file .net and, if it exists, the .cmp file<br />
<br />
In the event of a module being changed directly in Pcbnew the .cmp file is automatically updated avoiding in this way the requirement to run CvPcb again.<br />
<br />
The following figure illustrate the whole work-flow of Kicad and how intermediate files are obtained and used by the different software tools that made Kicad.<br />
<br />
<br />
[[Image:]]<br />
<br />
<br />
== Procedure for creating a printed circuit board ==<br />
After having created your schematic in Eeschema:<br />
<br />
* Generate the netlist using Eeschema.<br />
* Assign each component in you netlist file to the corresponding module (often called footptint) used on the printed circuit using Cvpcb.<br />
* Launch Pcbnew and read the modified Netlist, this will also read the file with the module selections.<br />
<br />
Pcbnew will then load automatically all the necessary modules. Modules can now be placed manually or automatically on the board and tracks can be routed.<br />
<br />
== Procedure for updating a printed circuit board ==<br />
If the schematic is modified (after a printed circuit board has been generated), the following steps must be repeated:<br />
<br />
* Generate a new netlist file using Eeschema.<br />
* If the changes to the schematic involve new components, the corresponding modules must be assigned using Cvpcb.<br />
* Launch Pcbnew and re-read the modified Netlist (this will also re-read the file with the module selections).<br />
<br />
Pcbnew will then load automatically any new module, add the new connections and remove redundant connections. This process is called forward annotation and is a very common procedure when a PCB is made and updated. <br />
<br />
== Reading netlist file - loading footprints ==<br />
=== Dialog box ===<br />
Accessible from the icon [[Image:]]<br />
<br />
<center>[[Image:]]</center><br />
<br />
=== Available options ===<br />
<br />
{| style="border-spacing:0;"<br />
| style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| Module Selection<br />
| style="border:0.05pt solid #000000;padding:0.097cm;"| Components and corresponding footprints on board link:<br />
<br />
normal link is Reference (normal option<br />
<br />
Timestamp can be used after reannotation of schematic, if the previous annotation was destroyed (special option)<br />
<br />
|-<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| Exchange Module:<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| If a footprint has changed in the netlist: keep old footprint or change to the new one.<br />
<br />
|-<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| Bad Tracks Deletion<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Keep all existing tracks, or delete erroneous tracks<br />
<br />
|-<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| Extra Footprints<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Remove footprints which are on board but not in the netlist.<br />
<br />
Footprint with attribute "Locked" will not be removed.<br />
<br />
|}<br />
=== Loading new footprints ===<br />
When new footprints are found in the netlist file, they will be automatically loaded and placed at coordinate (0,0).<br />
<br />
<center>[[Image:]]</center><br />
<br />
New footprints can be moved and arranged one by one. A better way is to automatically move (unstack) them:<br />
<br />
* Activate footprint mode<br />
<br />
<br />
{| style="border-spacing:0;"<br />
| style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| [[Image:]]<br />
| style="border:0.05pt solid #000000;padding:0.097cm;"| activate the "footprint mode".<br />
<br />
|-<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| [[Image:]]<br />
| style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| footprint mode activated.<br />
<br />
|}<br />
Move the mouse cursor to a suitable (free of component) area, and click on the right button<br />
<br />
<center>[[Image:]]</center><br />
<br />
* Move New Modules if there is already a board with existing footprints.<br />
* Move All Modules, the first time (when creating a board).<br />
<br />
The following screenshot shows the results.<br />
<br />
<center>[[Image:]]</center></div>Millo